Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
A conventional floating gate FLASH memory device includes a FLASH memory cell characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric, a floating gate, an intergate dielectric layer and a control gate. The gate dielectric of silicon dioxide (SiO2 gate dielectric) is formed on the semiconductor substrate. The floating gate (sometimes referred as the Acharge storing layer@) of n-type polysilicon is formed on the gate dielectric. The intergate dielectric layer (e.g., layers of SiO2, silicon nitride (Anitride@) and SiO2 and commonly referred to as an ONO layer) is formed on the floating gate. The control gate of n-type polysilicon is formed on the intergate dielectric layer. The floating gate formed on the SiO2 gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and drain are formed by dopant impurities introduced into the semiconductor substrate.
Generally speaking, a FLASH memory cell is programmed by inducing hot electron injection from a portion of the semiconductor substrate, such as the channel section near the drain, to the floating gate. Electron injection introduces negative charge into the floating gate. The injection mechanism can be induced by grounding the source and a bulk portion of the semiconductor substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates in the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a FLASH memory cell is programmed.
The act of discharging the floating gate of a FLASH memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase or negative gate erase), or between the floating gate and the semiconductor substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source and a zero or negative voltage to the control gate and zero voltage to the semiconductor substrate while floating the drain of the respective FLASH memory cell.
Turning to FIG. 1, FIG. 1 illustrates, in cross-section, a conventional semiconductor device 100 (i.e., a floating-gate transistor). Device 100 includes a semiconductor substrate 102 having an active region 104. A source 106 and a drain 108 are formed in the active region 104. A gate dielectric 110 is formed on the semiconductor substrate 102. A floating gate 112 is formed on the gate dielectric 110. The floating gate 112 defines the channel 114 between the source 106 and the drain 108. An intergate dielectric layer 116 is formed on the floating gate 112. The intergate dielectric layer 116 includes therein three layers which form an ONO structure. In the ONO structure of the intergate dielectric layer 116, a first layer 118 of silicon oxide is formed on the floating gate 112, a second layer 120 of silicon nitride is formed on the first layer 118, and a third layer 122, also silicon oxide, is formed on the second layer 120. A control gate 124 is formed on the ONO structure of the intergate dielectric layer 116. The gate dielectric 110, the floating gate 112, the intergate dielectric layer 116, and the control gate 124 form a vertical stack characteristic of a FLASH memory cell. Spacers 126 are formed on the sidewalls of the vertical stack. Isolation techniques that are known in the art may be used to electrically isolate the semiconductor device 100 from other semiconductor devices.
More recently dielectric memory cell structures, such as SONOS, have been developed. Turning to FIG. 2, FIG. 2 illustrates, in cross-section, a conventional SONOS-type memory device 200 suitable for use in a two-bit EEPROM device. Memory device 200 includes source/drain regions 206 and 208 located in an active region 204 of semiconductor substrate 202 and separated by a channel region 214. An intergate dielectric layer 216 (e.g., an ONO structure) overlies portions of the source region 206 and the drain region 208, as well as the channel region 214. A control gate electrode 224 is formed on the intergate dielectric layer 216. The control gate electrode 224 and the intergate dielectric layer 216 form a stacked-gate structure.
ONO structure 216 includes a first silicon oxide layer 218 overlying channel region 208. A silicon nitride layer 220 overlies first silicon oxide layer 218. A second silicon oxide layer (or top oxide layer) 222 overlies silicon nitride layer 220.
As is shown in FIG. 2, a device 200 is characterized by a vertical stack of an insulating tunnel oxide layer, a charge trapping nitride layer, an insulating top oxide layer, and a polysilicon control gate positioned on top of a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source diffusion and drain diffusion on opposing sides of the channel region.
Similar to a floating gate device, a SONOS memory cell, is programmed by inducing hot electron injection from the channel region to the nitride layer to create a non volatile negative charge within charge traps existing in the nitride layer. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate. The high voltage on the control gate inverts the channel region while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain sufficient energy to cross the 3.2 eV Si—SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region (or in a source charge storage region that is close to the source region if a source to drain bias is used) from which the electrons were injected. As such, the SONOS device can be used to store two bits of data, one in each of the charge storage regions per cell and are typically referred to as Mirror-BitJ SONOS-type flash memory devices.
Product development efforts in both floating gate and SONOS type memory device technology have focused on reducing cell dimensions and operation voltage, improving operation speed and data retention. As the cell size decreases, the thickness of the dielectric layers in the vertical stack need to decrease as well to maintain proper device operation. As floating gate widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device sub-threshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO2 layer thickness, operating voltage, depletion width, and junction depth, for example.
Unfortunately, thin SiO2 layers are more susceptible to stress induced leakage current (SILC), particularly SiO2 layers less than 50 Angstroms thick of the intergate dielectric layer. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such thin SiO2 layers by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the control gate and the floating gate, adversely affecting the operability of the device. For example, the leakage current increases exponentially for about a two-fold decrease in thickness of a SiO2 layer. The exponential increase in the SiO2 layer leakage current significantly affects the operation of semiconductor devices, particularly with regard to standby power, dissipation, reliability and lifetime.
Another disadvantage of thin SiO2 layers is that a breakdown of the SiO2 layers may also occur at even lower values of gate voltage, as a result of defects in the SiO2 layers. Such defects are unfortunately prevalent in relatively thin SiO2 layers.
Additionally, the deposition of thin SiO2 layers is more difficult to control due to inherent limitations of the deposition process. As devices are produced having layers with thicknesses on the order of a few monolayers, the thickness variation of these layers over a 200-mm or 300-mm silicon wafer is of substantial concern. A variation in thickness of only 1.0 Angstrom could result in changes in the device operating conditions. For example, the electron (or hole) mobility or the device transconductance may be affected. Additionally, variations in layer thickness make it extremely difficult to maintain device tolerances. Further, the layer thicknesses not only vary within a wafer, but also vary from lot-to-lot which affects the manufacturing of wafers.
Therefore, there exists a need in the art for a semiconductor device that has a dielectric layer which prevents or decreases the leakage current between a gate electrode and the semiconductor substrate. In semiconductor devices with multiple gates, there is a need to prevent the leakage current between a floating gate electrode and the semiconductor substrate and/or a control gate. Thus, the semiconductor devices can be further scaled without reducing the data retention of the finished device.